Renesas Electronics /R7FA6M1AD /SSIE0 /SSICR

Receive Enable

0 (0): Disables the receive operation.

1 (1): Enables the receive operation.

Transmit Enable

0 (0): Disables the transmit operation.

1 (1): Enables the transmit operation.

Mute EnableNOTE: When this module is muted, the value of outputting serial data is rewritten to 0 but data transmission is not stopped. Write dummy data to the SSIFTDR not to generate a transmit underflow because the number of data in the transmit FIFO is decreasing.

0 (0): This module is not muted.

1 (1): This module is muted.

Serial Oversampling Clock Division Ratio

0 (others): Settings other than above are prohibited.

0 (0x0): CLK

1 (0x1): CLK/2

2 (0x2): CLK/4

3 (0x3): CLK/8

4 (0x4): CLK/16

5 (0x5): CLK/32

6 (0x6): CLK/64

7 (0x7): CLK/128

8 (0x8): CLK/6

9 (0x9): CLK/12 (These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)

10 (0xA): CLK/24

11 (0xB): CLK/48(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)

12 (0xC): CLK/96(These bits are only settable for channel 0. Setting these bits in the register for channel 1 is prohibited.)

Serial Data Delay

0 (0): 1 clock cycle delay between SSIWS and SSIDATA

1 (1): No delay between SSIWS and SSIDATA

Parallel Data Alignment

0 (0): The lower bits of parallel data (SSITDR, SSIRDR) are transferred prior to the upper bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is left-aligned.(When data word length is 18, 20, 22, or 24 bits)

1 (1): The upper bits of parallel data (SSITDR, SSIRDR) are transferred prior to the lower bits.(When data word length is 8 or 16 bits) / Parallel data (SSITDR, SSIRDR) is right-aligned.(When data word length is 18, 20, 22, or 24 bits)

Serial Data Alignment

0 (0): Transmitting and receiving in the order of serial data and padding bits

1 (1): Transmitting and receiving in the order of padding bits and serial data

Serial Padding Polarity

0 (0): Padding bits are low.

1 (1): Padding bits are high.

Serial WS Polarity

0 (0): SSIWS is low for 1st channel, high for 2nd channel.

1 (1): SSIWS is high for 1st channel, low for 2nd channel.

Serial Bit Clock Polarity

0 (0): SSIWS and SSIDATA change at the SSISCK falling edge (sampled at the SCK rising edge).

1 (1): SSIWS and SSIDATA change at the SSISCK rising edge (sampled at the SCK falling edge).

Serial WS Direction NOTE: Only the following settings are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited.

0 (0): Serial word select is input, slave mode.

1 (1): Serial word select is output, master mode.

System Word LengthSet the system word length to the bit clock frequency/2 fs.

0 (others): Settings other than above are prohibited.

0 (000): 8 bits (serial bit clock frequency = 16fs )

1 (001): 16 bits (serial bit clock frequency = 32fs )

2 (010): 24 bits (serial bit clock frequency = 48fs )

3 (011): 32 bits (serial bit clock frequency = 64fs )

Data Word Length

0 (000): 8 bits

0 (others): Settings other than above are prohibited.

1 (001): 16 bits

2 (010): 18 bits

3 (011): 20 bits

4 (100): 22 bits

5 (101): 24 bits

Channels

0 (00): One channel

0 (others): Settings other than above are prohibited.

Idle Mode Interrupt Enable

0 (0): Disables an idle mode interrupt.

1 (1): Enables an idle mode interrupt.

Receive Overflow Interrupt Enable

0 (0): Disables an overflow interrupt.

1 (1): Enables an overflow interrupt.

Receive Underflow Interrupt Enable

0 (0): Disables an underflow interrupt.

1 (1): Enables an underflow interrupt.

Transmit Overflow Interrupt Enable

0 (0): Disables an overflow interrupt.

1 (1): Enables an overflow interrupt.

Transmit Underflow Interrupt Enable

0 (0): Disables an underflow interrupt.

1 (1): Enables an underflow interrupt.

Oversampling Clock Select

0 (0): AUDIO_CLK input

1 (1): Setting prohibited